The present invention relates generally to increasing data rates for data interfaces, and more specifically to adaptive 1 T/2T timing for memory controller interfaces.
Data rates in computer systems have been increasing at a dramatic rate for some years now. In particular, processor speeds have faithfully followed or exceed Moore's Law. But memory interface speeds have not kept track with this pace, and are quickly becoming a bottleneck in computer systems.
One reason that memory interface data rates have not increased at such a rate is that memory interface signals must drive large off-chip capacitive loads including several integrated circuits, whereas processors only drive signals on chip. Typically, a memory interface output cell drives a printed circuit board trace, one or more sockets, and one or more memory devices, such as dual-in-line memories (DIMMs). To make matters worse, each of these DIMMs typically include several individual dynamic random-access memories (DRAMs) devices.
This structure forms a distributed capacitance having a number of unmatched terminations. When an output circuit that is part of a memory interface drives this load, the resulting signal is corrupted by ringing, reflections, slowed edge rates, and other degradations.
This reduction in signal integrity is particularly disruptive at higher data rates. At slower data rates, these signals have more time following a transition for reflections and ringing to dissipate and settle. Accordingly, a methodology has been developed wherein the signals of a memory interface may be slowed.
This modification is referred to as 1T/2T timing. Simply stated, 1T timing is used when memory interface signals can be switched at their highest data speed without losing data caused by loss of signal integrity. 2T timing is used when data transferred at this rate could be lost due to this loss of signal integrity. A system BIOS (Basic Input Output System) often includes a setting that determines whether a memory interface uses 1T or 2T timing.
Since the data rate for 1T timing is twice that of 2T, it is desirable to operate at 1T timing as much as possible. Accordingly, what is needed are circuits, methods, and apparatus that enable a memory interface to adaptively operate at 1T timing instead of 2T timing when possible.